reducing the consumption power in flash adc using 65nm cmos technology

this paper presents a new method to reduce consumption power in flash adc in 65nm cmos technology. this method indicates a considerable reduction in consumption power, by removing comparators memories. the simulations used a frequency of 1 ghz, resulting in decreased consumption power by approximately 90% for different processing corners. in addition, in this paper the proposed method was designed using interpolation technique for purpose of promoting the performance as well as decreasing the class of chip. the simulation results indicate that the consumption power for interpolation technique was decreased by approximately 5% compared to the proposed method. also, we compare the results of the proposed technique with those of convertors frequently referred in other studies. the results show that the consumption power is considerably decreased, using the proposed technique.